This invention relates to an internal voltage generating circuit for generating voltages used in, for example, a semiconductor memory device, and more particularly to an internal voltage generating circuit for generating different voltages.
In a nonvolatile semiconductor memory, such as a flash EEPROM, several types of voltages differing in level are applied to a memory cell, depending on the operation, such as a read operation, a program (write) operation, or an erase operation.
FIG. 1 shows the relationship between a series of operations in a nonvolatile semiconductor memory and the voltages applied to the control gate of a memory cell in the respective operations. As shown in FIG. 1, in addition to a read operation, a program (write) operation, and an erase operation, a verify operation is performed after a program or erase operation to cause the threshold value of the memory cell to converge in a certain range in the nonvolatile semiconductor memory.
Furthermore, to sense the overerased state after the data in the selected block in a memory cell array has been erased all at once, an overerase verify operation is performed using an overerase verify voltage for sensing an overerased cell. When an overerased cell has been sensed in the overerase verify operation, the overerased cell is subjected to weak programming (or a weak write operation). The weak programming is a method of controlling the threshold distribution of the cell into a narrow range of 0.5 to 1.0V. In the method, writing is done by changing the voltage applied to the control gate of the cell little by little. Specifically, when an erased cell has been sensed in an overerase verify operation, the overerased cell is subjected to weak programming at a first gate voltage. Thereafter, the threshold value of the cell is verified again. If the threshold value of the cell has not shifted to the target range of threshold value distribution, the cell is subjected to weak programming again at a voltage higher than the first gate voltage by a voltage of .DELTA.V. Repeating such an operation causes the threshold voltage of the cell to converge into the target range of threshold value distribution.
As described above, the nonvolatile semiconductor memory requires many voltages of different levels according to various types of operations.
In recent years, nonvolatile semiconductor memory devices have been designed to use a single power source. For this reason, the aforementioned various types of voltages used in a nonvolatile semiconductor memory are generated at a voltage generating circuit provided in a chip. The voltage generating circuit is composed of a booster circuit for boosting a supply voltage supplied from the outside and an internal voltage generating circuit for generating an internal voltage of a desired level from the output voltage of the booster circuit.
FIG. 2 shows an internal voltage generating circuit disclosed in Japanese Patent Application No. 8-162753 (Jpn. Pat. Appln. KOKAI Publication No. 10-011987). The internal voltage generating circuit, which is a voltage generating circuit of a so-called voltage-summing type, is capable of generating a voltage of a desired level according to the digital signal applied to a decoder. Specifically, in FIG. 2, a resistance string RS is composed of resistances R0 to R15 connected in series. The resistance string RS is connected via resistance Rstd to the ground. Switches S0 to S15 are connected to the junction nodes of an output node N1 and the respective resistances R0 to R15. The switches S0 to S15 are selectively turned on by the output signal of a decoder 17 to which digital signals A0, A1, A2, and A3 are supplied. Differential amplifiers 11 and 12 compare the voltage at node N2 to which the resistance string RS and resistance Rstd are connected with a reference voltage Vref. When the voltage at node N2 is lower than the reference voltage Vref, the differential amplifier 11 goes high at its output terminal. When the voltage at node N2 is higher than the reference voltage Vref, the differential amplifier 12 goes high at its output terminal.
The gate of an n-channel MOS transistor 13 is connected to the output of the differential amplifier 11 and is controlled by the output signal of the differential amplifier 11. A p-channel MOS transistor 14 is connected between a power supply terminal VPP and one end of the current path of the transistor 13 and supplies current to the transistor 13. A p-channel MOS transistor 15 connected between the power supply terminal VPP and the output node N1, together with the transistor 14, constitutes a current-mirror circuit. The transistor 15 pulls up the potential at the output node N1 according to the output signal of the differential amplifier 11. An n-channel MOS transistor 16 has its gate connected to the output terminal of the differential amplifier 12 and its current path connected between the output node N1 and the ground. When the output signal of the differential amplifier 12 is at the high level, the transistor 16 turns on, pulling down the potential at the output node N1. A booster circuit (not shown) supplies a voltage boosted from an external supply voltage to the power supply terminal VPP.
With this configuration, when the switch is changed according to a digital signal and the potential at node N2 is made lower than the reference voltage Vref, the output signal of the differential amplifier 11 goes to the high level and the output signal of the differential amplifier 12 goes to the low level. As a result, the transistor 13 turns on, the transistor 16 turns off, and the transistor 15 turns on. This causes the output node N1 to be charged via the transistor 15, raising the output voltage Vout. When the potential at the node N2 has become higher than the reference voltage Vref as a result of the rise of the output voltage Vout, the charging of the output node N1 is stopped.
In addition, when the switch is changed according to the digital signal and the potential at the node N2 is made higher than the reference voltage Vref, the output signal of the differential amplifier 11 goes to the low level and the output signal of the differential amplifier 12 goes to the high level. As a result, the transistor 13 turns off, the transistor 16 turns on, and the transistor 15 turns off. This causes the output node N1 to be discharged via the transistor 16, reducing the output voltage Vout. When the potential at the node N2 has become lower than the reference voltage Vref as a result of the drop of the output voltage Vout, the discharging of the output node N1 is stopped.
Although the internal voltage generating circuit can generate a required voltage, it has the following problem: as the number of output voltages increases, the number of resistances constituting the resistance string RS, the number of switches, and the number of decoders increase and therefore the area of the circuit increases. For example, when the number of output voltages is needed to be 32, 32 resistances are needed for the resistance string RS and 32 switches are required to switch these resistances. Furthermore, 32 5-bit decoders 17 for decoding a 5-bit digital signal are necessary to control the switches.
In general, when the number of output voltages is 2.sup.N, 2.sup.N resistances are required and 2.sup.N N-input decoders for decoding an N-bit digital signal are needed. As the value of N increases, the number of elements, including decoders and resistances, increases sharply and the area the pattern of those elements occupy in the chip increases, which makes the circuit design difficult. Moreover, the flexibility in changing the pattern decreases for variations in the value of resistance caused in the manufacture, which makes it difficult to change the design to adjust the value of resistance. Consequently, fine adjustment of the output voltage cannot be made.
To overcome the problem in the voltage-summing voltage generating circuit, a current-summing voltage generating circuit has been developed.
FIG. 3 shows a current-summing voltage generating circuit disclosed in Japanese Patent Application No. 9-277035 (Jpn. Pat. Appln. KOKAI Publication No. 11-122109). In FIG. 3, a ladder resistance circuit 21 is composed of resistances R (each having the value R) connected in series and resistances 2R (each having the value 2R) one end of each of which is connected to the corresponding junctions of the resistances R. A switch circuit 22 is connected to the ladder resistance circuit 21. The switch circuit 22 is composed of n-channel MOS transistors Q01, Q11, Q21, Q31, and Q41, and n-channel MOS transistors Q02, Q12, Q22, Q32, and Q42. Each of the n-channel MOS transistors Q01, Q11, Q21, Q31, and Q41 has one end of its current path connected to the other end of the corresponding resistance 2R and the other end of its current path connected to a first node X. Each of the n-channel MOS transistors Q02, Q12, Q22, Q32, and Q42 has one end of its current path connected to the other end of the corresponding resistance 2R and the other end of its current path connected to a first node Y. Digital signals (address signals) A0 to A4 are supplied to the gates of the transistors Q01 to Q41, respectively. Address signals /A0 to /A4 (the mark/represents an inverted signal) are supplied to the gates of the Q02 to Q42, respectively. A load resistance RD is connected between the junction node A and the ground.
A differential amplifier 23 compares a reference voltage Vref with the voltage at node X. The output terminal of the differential amplifier 23 is connected to the gate of a transistor Q61. A power source VPP is supplied to the source of the transistor Q61, whose drain is connected to an output node. The output node N1 is connected to the node x via a load resistance RL.
A current source circuit 24 is composed of a differential amplifier 25 and a transistor Q62 whose gate is connected to the output of the differential amplifier 25. The differential amplifier 25 compares the reference voltage Vref with the voltage at the first node Y. A supply voltage Vcc is supplied to the source of the transistor Q62, whose drain is connected to the first node Y.
The operation of the current-summing voltage generating circuit constructed as described above will be explained briefly. When the individual transistors Q01 to Q42 in the switch circuit 22 are changed according to the address signals A0 to /A4, the resistance value of the latter resistance circuit 21 connected to the load resistance RL changes. As a result, the current flowing through the load resistance RL changes. In response to this, the differential amplifier 23 and transistor Q61 are operated, which performs control so that the potential at the first node x may become equal to the reference voltage Vref. In the current source circuit 24, the differential amplifier 25 and transistor Q62 control the potential at the second node Y so that it may become equal to the reference voltage Vref. As a result, when the switch circuit 22 is switched according to the address signals A0 to A4, /A0 to /A4, the potentials at the first node X and second node Y are controlled so that they may be constantly equal to the reference voltage Vref. If this condition is satisfied, the combined resistance can be calculated as described below.
It is assumed that, of the nodes in the ladder resistance circuit 21, current I3 flows from, for example, node E. At this time, the combined resistance obtained when the node Y side is viewed from node E is R+R=2R, which is equal to the resistance value obtained when the resistance 2R side is viewed from node E. Thus, the current I4 flowing from the node F side to the node E side is equal to the current I4' flowing through the transistor Q41 and resistance 2R into node E or the current I4' flowing from the second node Y through the transistor Q42 and resistance 2R to node E when the transistor Q42 is on. Specifically, the relationship between those currents is expressed by equation (1):
I.sub.4 '=I.sub.4 =I.sub.3 /2 (1)
Next, consider a node D in the ladder resistance circuit 21. The combined resistance from the node D to node E side is 2R as expressed by equation (2): ##EQU1##
Therefore, the value of the combined resistance at node D on the node E side is equal to the value of the resistance on the resistance 2R side. Consequently, the current I3 flowing from the node E side to the node D side is equal to the current I3' flowing from the first node x through the transistor Q31 and resistance 2R into node D when the transistor Q31 is on or to the current I3' flowing from the second node Y through the transistor Q32 and resistance 2R into node D when the transistor Q32 is on. Specifically, if the current I2 flows into node D, the relationship between those currents is expressed by equation (3): EQU I.sub.3 '=I.sub.3 =I.sub.2 /2 (3)
As described above, the combined resistance at each node in the ladder resistance circuit 21 is considered in sequence. Finally, the value of the combined resistance from the node A to node F side is represented by a continued fraction expressed as equation (4) and equals the value of the resistance on the resistance 2R side: ##EQU2##
Therefore, at each node, the current flowing toward the ground potential side is what is obtained by adding the same current flowing from each of the node F side and resistance 2R side.
Specifically, if the current flowing to the load resistance RD is Iall, the currents flowing through the individual resistances R from node A toward the node F side are expressed as Iall/2, Iall/4, Iall/8, . . . , Iall/32 in this order. These currents are added and the resulting current is converted by the ladder resistance circuit 21 into a voltage. Thus, the output voltage Vout outputted at the output node N1 is expressed by equation (5): ##EQU3##
where Ai is the address signals A0 to A4 and calculations are done, provided that when Ai is at the high level, it has a "1" and when Ai is at the low level, it has a "0".
In the current-summing voltage generating circuit constructed as described above, the switch circuit 22 connected to the ladder resistance circuit 21 is controlled directly by the address signals. As a result, many decoders are not needed and therefore the pattern area is reduced. Since two types of resistances, R and 2R, are used in the ladder resistance circuit 21, the circuit is designed easily. Consequently, the voltage generating circuit is more effective as the number of bits in the digital signals increases.
In the conventional current-summing voltage generating circuit, however, the output voltage Vout is changed by changing the value of the current flowing through load resistance RL, as seen from equation (5). As a result, as the current flowing through the load resistance is increased, the output voltage rises.
FIG. 4 shows the relationship between the current flowing through the load resistance RL and the output voltage Vout. In a case where setting is done so that the maximum current Imax may flow through the load resistance RD in the effective range when the output voltage Vout is the highest, the current flowing through the load resistance RL is smaller than the minimum current Imin in the effective range when the output voltage Vout is the lowest, as shown by characteristic P1. Thus, it takes a long time to charge and discharge the output node via the load resistance RL, lowering the response performance. As described earlier, for example, when weak programming is effected, it is necessary to set the potential of the word line quickly to a desired potential. When the response performance is low as described above, it is difficult to secure the desired operating speed.
On the other hand, in a case where setting is done so that the minimum current Imin may flow through the load resistance RL in the effective range when the output voltage Vout is the lowest, the current flowing through the load resistance RL is larger than the maximum current Imax in the effective range when the output voltage Vout is the highest, as shown by characteristic P2. Thus, the drawn current becomes large, making it difficult to use the circuit in, for example, a battery-driven portable device.
In addition, the booster circuit for supplying the supply voltage VPP to the supply voltage generating circuit is composed of a so-called charge pump circuit. The charge pump circuit is composed of, for example, transistors diode-connected, and capacitors one end of each of which is connected to the corresponding junction of the transistors and to the other end of which a signal from an oscillator is supplied. As the charge pump circuit generates a higher voltage, its current supplying capability decreases. Thus, the setting as shown by characteristic P2 has a significant effect on the design of the booster circuit.